adg738/ADG739 a rev. prc august 99 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 analog devices, inc., 1999 cmos, low voltage, serially controlled matrix switches preliminary technical data preliminary technical data features three wire serial interface +2.7 v to +5.5 v single supply low on resistance (4 w w w w w ) low on resistance flatness low leakage single 8 to 1 multiplexer adg738 dual 4 to 1 multiplexer ADG739 power on reset fast switching times low power consumption ttl/cmos compatible applications data acquisition systems communication systems relay replacement audio and video switching general description the adg738 and ADG739 are cmos analog matrix switches with a serially controlled three wire interface. the adg738 is an 8 channel matrix switch, while the ADG739 is a dual 4 channel matrix switch. on resistance is closely matched between switches and very flat over the full signal range. the adg738 and ADG739 utilize a three wire serial interface that is compatible with spi tm , qspi tm and microwire tm interface standards. the output of the shift register dout enables a number of these parts to be daisy chained. on power up of the devices, the internal shift register contains all zeros and all switches are in the off state. each switch conducts equally well in both direction when on, making these parts suitable for both multiplexing and demultiplexing applications. as each switch is turned on or off by a seperate bit, these parts can also be configured as a type of switch array, where any, all or none of the 8 switches may be closed at any time. the input signal range extends to the supply rails. product highlights 1. three wire serial interface. 2. single supply operation. the adg738 and ADG739 are fully specified and guaranteed with +3 v and +5 v supply rails. 3. low r on (4 w ). 4. any configuration of switches may be on or off at any one time. 5. break before make switching action. 6. small 16 lead tssop package. functional block diagrams spi and qspi are trademarks of motorola, inc. microwire is a trademark of national semiconductor corporation. s1 s8 sclk d din sync logic adg738 s1a sclk da din s4a s1b s4b db ADG739 logic reset dout dout sync all channels exhibit break before make switching action preventing momentary shorting when switching channels. the adg738 and ADG739 are available in 16 lead tssop package.
C2C rev. prc adg738/ADG739Cspecifications 1 (v dd = +5 v 10%, gnd = 0 v. all specifications C40c to +85c unless otherwise noted) preliminary technical data b version C40c parameter +25 o c to +85c units test conditions/comments analog switch analog signal range 0 v to v dd v on-resistance (r on ) 2.5 w typ v s = 0 v to v dd , i s = 10 ma; 4 4.5 w max test circuit 1; on-resistance match between 0.1 w typ channels ( d r on ) 0.4 w max v s = 0 v to v dd , is = 10 ma; on-resistance flatness (r flat(on) ) 0.75 w typ v s = 0 v to v dd , i s = 10 ma; 1.2 w max leakage currents source off leakage i s (off) 0.01 na typ v d = 4.5 v/1 v, v s = 1 v/4.5 v; 0.1 0.3 na max test circuit 2; drain off leakage i d (off) 0.01 na typ v d = 4.5 v/1 v, v s = 1 v/4.5 v; 0.1 0.3 na max test circuit 3; channel on leakage i d (on) 0.01 na typ v d = v s = 1 v, or 4.5v; 0.1 0.3 na max test circuit 4; digital inputs input high voltage, v inh 2.4 v min input low voltage, v inl 0.8 v max input current, i inl or i inh 0.005 a typ v in = v inl or v inh 0.1 a max c in , digital input capacitance 3 pf typ digital outputs dout output high voltage v dd max dout output low voltage 0.4 max dynamic characteristics 2 t on 30 ns typ r l = 300 w , c l = 35 pf; t b d ns max v s = 3 v, test circuit 5; t off 21 ns typ r l = 300 w , c l = 35 pf; t b d ns max v s = 3 v, test circuit 5; break-before-make time delay, t d 15 ns typ r l = 300 w , c l = 35 pf 1 ns min v s = 3.5 v, test circuit 6 charge injection 5 pc typ v s = 2 v, r s = 0 w , c l = 1 nf; test circuit 8; off isolation -60 db typ r l = 50 w , c l = 5 pf, f = 10 mhz; test circuit 9; channel to channel crosstalk -60 db typ r l = 50 w , c l = 5 pf, f = 10 mhz; test circuit 10; -3 db bandwidth 200 mhz typ r l = 50 w , c l = 5 pf, test circuit 11; c s (off) tbd pf typ c d (off) tbd pf typ c d , c s (on) t b d pf typ power requirements v dd = +5.5 v i dd 10 a typ digital inputs = 0 v or 5.5 v tbd a max notes 1 temperature range is as follows: b version: C40c to +85c. 2 guaranteed by design, not subject to production test. specifications subject to change without notice.
C3C rev. prc adg738/ADG739 preliminary technical data preliminary technical data b version C40c parameter +25 o c to +85c units test conditions/comments analog switch analog signal range 0 v to v dd v on-resistance (r on ) 4.5 5 w typ v s = 0 v to v dd , i s = 10 ma; 8 w max test circuit 1; on-resistance match between channels ( d r on ) 0.1 w typ v s = 0 v to v dd , is = 10 ma; 0.4 w max on-resistance flatness (r flat(on) ) 2.5 w max v s = 0 v to v dd , i s = 10 ma; leakage currents v dd = +3.3 v source off leakage i s (off) 0.01 na typ v s = 3 v/1 v, v d = 1 v/3 v; 0.1 0.3 na max test circuit 2; drain off leakage i d (off) 0.01 na typ v s = 1 v/3 v, v d = 3 v/1 v; 0.1 0.3 na max test circuit 3; channel on leakage i d (on) 0.01 na typ v s = v d = +1 v or +3 v; 0.1 0.3 na max test circuit 4; digital inputs input high voltage, v inh 2.0 v min input low voltage, v inl 0.4 v max input current, i inl or i inh 0.005 a typ v in = v inl or v inh 0.1 a max c in , digital input capacitance 3 pf typ digital outputs dout output high voltage v dd max dout output low voltage 0.4 max dynamic characteristics 2 t on 35 ns typ r l = 300 w , c l = 35 pf; t b d ns max v s = 2 v, test circuit 5; t off 27 ns typ r l = 300 w , c l = 35 pf; t b d ns max v s = 2 v, test circuit 5; break-before-make time delay, t d 15 ns typ r l = 300 w , c l = 35 pf 1 ns min v s = 2 v, test circuit 6 charge injection 5 pc typ v s = 1.5 v, r s = 0 w , c l = 1 nf; test circuit 8; off isolation -60 db typ r l = 50 w , c l = 5 pf, f = 10 mhz; test circuit 9; channel to channel crosstalk -60 db typ r l = 50 w , c l = 5 pf, f = 10 mhz; test circuit 10; -3 db bandwidth 200 mhz typ r l = 50 w , c l = 5 pf, test circuit 11; c s (off) tbd pf typ c d (off) tbd pf typ c d , c s (on) t b d pf typ power requirements v dd = +3.3 v i dd 10 a typ digital inputs = 0 v or 3.3 v tbd a max notes 1 temperature ranges are as follows: b versions: C40c to +85c. 2 guaranteed by design, not subject to production test. specifications subject to change without notice. (v dd = 3v 10%, gnd = 0 v. all specifications -40c to +85c , unless otherwise noted.) specifications 1
C4C rev. prc preliminary technical data preliminary technical data adg738/ADG739 timing characteristics 1,2 parameter limit at t min , t max units conditions/comments t 1 33 ns min sclk cycle time t 2 13 ns min sclk high time t 3 13 ns min sclk low time t 4 0 ns min sync to sclk active edge setup time t 5 5 ns min data setup time t 6 4.5 ns min data hold time t 7 0 ns min sclk falling edge to sync rising edge t 8 33 ns min minimum sync high time t 9 20 ns min sclk rising edge to dout valid notes 1 see figure 1. 2 all input signals are specified with tr =tf = 5ns (10% to 90% of v dd ) and timed from a voltage level of (v il + v ih )/2. specifications subject to change without notice. figure 1. 3-wire serial interface timing diagram. (v dd = +2.5v to +5.5v. all specifications -40c to +85c , unless otherwise noted.) sclk t 1 sync din db7 db0 t 2t 3 t 4 t 6 t 5 t 7 t 8 db7 db0 t 9 dout
adg738/ADG739 C5C rev. prc preliminary technical data preliminary technical data pin configurations pin function description adg738 ADG739 mnemonic function 1 1 sclk serial clock input. data is clocked into the input shift register on the falling edge of the serial clock input. these devices can accomodate serial input rates of up to 30mhz. 2- reset active low control input that clears the input register and turns all switches to the off condition. 3 3 d i n serial data input. data is clocked into the 8-bit input register on the falling edge of the serial clock input. 4,5,6,7 4,5,6,7 sxx source. may be an input or output. 8 8,9 d x drain. may be an input or output. 9,10,11,12 10,11,12,13 s x x source. may be an input or output. 13 14 v dd power supply input. these parts can be operated from a supply of +2.5v to +5.5v. 14 15 gnd ground reference. 15 16 d o u t data output. this allows a number a parts to be daisy chained. data is clocked out of the input shift register on the rising edge of sclk. 16 2 sync active low control input. this is the frame synchronization signal for the input data. when sync goes low, it powers on the sclk and din buffers and the input shift register is enabled. data is transferred on the falling edges of the following 8 clocks. taking sync high, updates the switches. ordering guide model temperature range package description package option adg738bru -40 o c to +85 o c thin shrink small outline package (tssop) ru-16 ADG739bru -40 o c to +85 o c thin shrink small outline package (tssop) ru-16 sclk reset s2 s3 s4 s1 d 1 2 16 15 5 6 7 12 11 10 3 4 14 13 8 9 top view (not to scale) adg738 sync dout s5 s6 s7 gnd v dd s8 din sclk sync din dout gnd s2a s3a s4a s2b s3b s4b s1a v dd s1b da db 1 2 16 15 5 6 7 12 11 10 3 4 14 13 89 top view (not to scale) ADG739
C6C rev. prc preliminary technical data preliminary technical data adg738/ADG739 r on ohmic resistance between d and s. r flat(on) flatness is defined as the difference between the maximum and minimum value of on- resistance as measured over the specified analog signal range. i s (off) source leakage current with the switch off. i d (off) drain leakage current with the switch off. i d , i s (on) channel leakage current with the switch on. v d (v s ) analog voltage on terminals d, s. c s (off) off switch source capacitance. measured with reference to ground. c d (off) off switch drain capacitance. measured with reference to ground. c d ,c s (on) on switch capacitance. measured with reference to ground. c in digital input capacitance. t on delay between applying the digital control input and the output switching on. see test circuit 4. terminology t off delay between applying the digital control input and the output switching off. off isolation a measure of unwanted signal coupling through an off switch. crosstalk a measure of unwanted signal which is coupled through from one channel to another as a result of parasitic capacitance. charge a measure of the glitch impulse transferred injection from the digital input to the analog output during switching. bandwidth the frequency at which the output is attenuated by -3dbs. on response the frequency response of the on switch. on loss the voltage drop across the on switch seen on the on response vs. frequency plot as how many dbs the signal is away from 0db. v inl maximum input voltage for logic 0. v inh minimum input voltage for logic 1. i inl (i inh ) input current of the digital input. i dd positive supply current. absolute maximum ratings 1 (t a = +25c unless otherwise noted) v dd to gnd C0.3 v to +7 v analog, digital inputs 2 -0.3v to v dd +0.3 v or 30 ma, whichever occurs first peak current, s or d 100ma (pulsed at 1 ms, 10% duty cycle max) continuous current, each s 30ma continuous current d, adg729 80ma continuous current d, adg728 120ma operating temperature range industrial (b version) C40c to +85c storage temperature range C65c to +150c junction temperature +150c tssop package, power dissipation mw q ja thermal impedance 150.4c/w q jc thermal impedance 27.6c/w lead temperature, soldering vapor phase (60 sec) +215c infrared (15 sec) +220c esd 2kv notes 1 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. only one absolute maximum rating may be applied at any one time. 2 overvoltages at in, s or d will be clamped by internal diodes. current should be limited to the maximum ratings given. caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the adg738/ADG739 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
adg738/ADG739 C7C rev. prc preliminary technical data preliminary technical data general description the adg738 and ADG739 are serially controlled, 8 channel and dual 4 channel matrix switches respectively. while providing the normal multiplexing and demultiplexing functions, these parts also provide the user with some more flexibility as to where their signal may be routed. each bit of the 8 bit serial word corresponds to one switch of the part. a logic 1 in the particular bit position turns on the switch, while a logic 0 turns the switch off. because each switch is independently control- led by an individual bit, this provides the option of having any, all or none of the switches on. this feature may be particularly useful in the demultiplexing application where the user may wish to direct one signal from the drain to a number of outputs (sources). care must be taken, how- ever, in the multiplexing situation where a number of inputs may be shorted together, (only separated by the small on resistance of the switch). power on reset on power up of the device, all switches will be in the off condition and the internal shift register is filled with zeros and will remain so until a valid write takes place. s8 s7 s6 s5 s4 s3 s2 s1 db0 (lsb) db7 (msb) data bits serial interface the adg738 and ADG739 have a three wire serial inter- face ( sync , sclk, and din), which is compatible with spi, qspi, microwire interface standards and most dsps. figure 1 shows the timing diagram of a typical write sequence. data is written to the 8-bit shift register via din under the control of the sync and sclk signals. data may be written to the shift register in more or less than 8 bits. in each case the shift register retains the last eight bits that were written. when sync goes low, the input shift register is enabled. data from din is clocked into the shift register on the falling edge of sclk. each bit of the eight bit word corresponds to one of the eight switches. figure 2 shows the contents of the input shift register. data appears on the dout pin on the rising edge of sclk suitable for daisy chaining, delayed of course by eight bits. when all eight bits have been written into the shift register, the sync line is brought high again. the switches are updated with the new configuration and the input shift register is disabled. with sync held high, any further data or noise on the din line will have no effect on the shift register. figure 2. input shift register contents test circuits tbd
adg738/ADG739 C8C rev .prc printed in u.s.a. 00000000 outline dimensions dimensions shown in inches and (mm). preliminary technical data preliminary technical data 16-lead tssop (ru-16) 16 9 8 1 0.201 (5.10) 0.193 (4.90) pin 1 seating plane 0.006 (0.15) 0.002 (0.05) 0.0118 (0.30) 0.0075 (0.19) 0.0256 (0.65) bsc 0.0433 (1.10) max 0.0079 (0.20) 0.0035 (0.090) 0.028 (0.70) 0.020 (0.50) 8 0 0.177 (4.50) 0.169 (4.30) 0.256 (6.50) 0.246 (6.25)
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